1. Field of the Invention
The present invention relates to an etching method.
2. Description of the Related Art
A process to form a Through-Silicon Via (TSV) for a three-dimensional packaging includes steps of reversing a substrate, to be processed, in upward and downward directions and bonding the substrate with a support substrate. In these steps, a front surface side of the substrate in which a semiconductor device such as the TSV or the like is formed is bonded to the support substrate by an adhesive agent, a back side surface of the substrate is grinded to make the substrate thinner, and then a silicon layer of the substrate is etched by plasma via a mask having a predetermined pattern. According to the etching method, it is necessary to optimize a process condition regarding positions of the semiconductor device, the adhesive agent, and the like when etching the substrate from the back side surface thereof because the bonded structure of the substrate, which is to be etched, has a specific structure. Furthermore, it is important to optimize a process condition for actualizing a high etching rate and uniformity in etching shapes, and suppressing notching generated at an interface between the silicon layer and an insulating film provided below the silicon layer.
For such a process condition for etching silicon, for example, non-Patent Document 1 discloses a relationship between pressure conditions and notching when a desired high frequency for bias (a high bias frequency) in Electron Cyclotron Resonance (ECR) is applied. Further, non-Patent Document 2 discloses a relationship between ion densities in plasma and notching.
However, non-Patent Documents 1 and 2 do not disclose an optimization of a process condition when etching a silicon layer of a substrate, to be processed, that is a bonded structure of the substrate, reversed in upward and downward directions, and a support substrate.
Further, when etching the substrate of the bonded structure, if a reaction product is deposited on an etched surface of the substrate, there is a possibility that an influence occurs on the semiconductor device formed in the substrate or the adhesive agent that bonds the support substrate when removing the deposited reaction product. Thus, it is desired to provide an optimization of a process condition in which a reaction product caused by etching is not generated.
In TSV etching, mainly, it is necessary to actualize a high silicon etching rate and suppress notching generated at an interface between a silicon layer and an insulating film provided below the silicon layer. Then, as a general etching shape, there may be a case that an insulating film (generally, silicon oxide film (SiO2)) is exposed at a bottom of a via generated by etching.
In a general silicon etching, a high silicon etching rate is actualized by applying a high power or the like, by increasing selectivity between a resist film and a silicon film by depositing a deposited component of a kind of oxide film on the resist film, prior to etching or at the same time with etching. However, there is a problem wherein gas for removing the resist after etching the silicon etches the insulating film exposed at the bottom of the via.